An FPGA Based Hardware Algorithm Implementation for Cascaded Multilevel Inverters

In recent years, Field Programmable Gate Arrays (FPGAs) have become key components in implementing high performance digital signal processing (DSP) systems, especially in the areas of digital communications, networking, video, and imaging, but its potential is not fully utilized in the area of power control and conversions. FPGA far exceeds that of a microprocessor or DSP processor running at clock rates two to ten times that of the FPGA. Coupled with a capability for implementing highly parallel arithmetic architectures, this makes the FPGA ideally suited for creating highperformance custom data path processors for tasks such as digital filtering, fast Fourier transforms, and forward error correction. In this paper a XILINX FPGA based multilevel PWM three phase inverter was constructed by adding bidirectional switches to the conventional bridge topology. The inverter can produce three and five different output voltage levels across the load. FPGA is used as a SVPWM generator to apply the appropriate signals to inverter switches. In addition to XILINX FPGA, Matlab/Simulink ® , system generator software was used for simulation and verification of the proposed circuit before implementation, simulation, and experimental results show that both are in close agreement. The present PWM signal generation scheme can be used for any multilevel inverter configuration. (